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71M6543F/71M6543G Data Sheet
6.4
6.4.1
Performance Specifications
Input Logic Levels
Table 89: Input Logic Levels
Digital high-level input voltage , V IH
Digital low-level input voltage , V IL
Parameter
1
1
Input pullup current, I IL
E_RXTX, E_RST, E_TCLK
OPT_RX, OPT_TX
SPI_CSZ (SEGDIO36)
Other digital inputs
Input pull down current, I IH
ICE_E, RESET, TEST
Other digital inputs
Condition
VIN=0 V,
ICE_E=3.3 V
VIN=V3P3D
Min
2
10
10
10
-1
10
-1
Typ
0
0
Max
0.8
100
100
100
1
100
1
Unit
V
V
μA
μA
μA
μA
μA
μA
Note:
1. In battery powered modes, digital inputs should be below 0.1 V or above VBAT – 0.1 V to
minimize battery current.
6.4.2
Output Logic Levels
Table 90: Output Logic Levels
Parameter
Digital high-level output voltage
V OH
Digital low-level output voltage
V OL
Condition
I LOAD = 1 mA
I LOAD = 15 mA
(see notes 1, 2)
I LOAD = 1 mA
I LOAD = 15 mA
(see note 1)
Min
V3P3D–0.4
V3P3D-0.6
0
0
Typ
Max
0.4
0.8
Unit
V
V
V
V
Note:
1. Guaranteed by design; not production tested.
2. Caution: The sum of all pull up currents must be compatible with the on-resistance of the
internal V3P3D switch. See 6.4.6 V3P3D Switch on page 136 .
132
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